O u t p u t = A ∧ A ¯ changes from false to true then a brief period will ensue during which both inputs are true, and so the gate's output will also be true. Certain systems can tolerate such glitches but if this output functions as a clock signal for further systems that contain memory, for example, the system can rapidly depart from its designed behaviour (in effect, the temporary glitch becomes a permanent glitch).Ĭonsider, for example, a two-input AND gate fed with the following logic: The output may, for a brief period, change to an unwanted state before settling back to the designed state. The inputs to the gate can change at slightly different times in response to a change in the source signal. 3.3 Example definitions of data races in particular concurrency modelsĪ typical example of a race condition may occur when a logic gate combines signals that have traveled along different paths from the same source.1.2 Static, dynamic, and essential forms.
